Advances in semiconductor processing have demanded ever-increasing high functional density with continuous size scaling. This scaling process has led to the adoption of high-k gate dielectrics and metal gate electrodes in metal gate stacks in semiconductor devices.
High-k gate dielectrics can offer a way to scale the thickness of the gate dielectric with acceptable gate leakage current. The use of high-k gate dielectrics is often accompanied by a metal gate electrode, since thin gate dielectric layers may cause poly depletion, affecting the device operation and performance. Metal gate electrodes further have an advantage of higher electrical conductance, as compared to poly gates, and thus can improve signal propagation times.
The manufacture of devices using high-k dielectric materials entails the integration and sequencing of many unit processing steps (some of them new) since high-k gate dielectrics are more sensitive to process conditions than silicon dioxide. Gate stacks formed using high-k dielectric materials often include multiple interfaces between the various layers. These interfaces can affect the final device performance. For example, different combinations of high-k dielectric materials and metal electrode materials can exhibit different device characteristics such as effective work function, flatband voltage, dielectric constant, capacitance, etc. affecting the performance of the high-k gate structures. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as power efficiency, signal propagation, and reliability.
Therefore, there is a need to develop and investigate the influence of interface characteristics on electrical properties such as effective work function for the manufacture of high-k devices in an efficient manner.